MEMS (Micro Electro Mechanical System) packages can contain many electrical and mechanical components in one device. Through various micro process techniques, a MEMS package is typically formed by disposing a micro-electromechanical element on a chip/die and then packaging the MEMS chip/die with a protection mask or an underfill to protect it from mechanical damage and hostile environments.
The package serves to integrate all of the components required for a system application in a manner that minimizes size, cost, mass and complexity. The three main functions of the MEMS package include: mechanical support, protection from the environment, and electrical connection to other system components. FIGS. 1A through 1D are cutaway views depicting several conventional package structures having micro-electromechanical, MEMS elements formed thereon.
The illustration of FIG. 1A is disclosed by U.S. Pat. No. 6,809,412, characterized in that a chip 14 having a micro-electromechanical element 141 formed thereon is disposed on a substrate 10, wherein the chip 14 is electrically connected to the substrate 10 by bonding wires 11, and finally a glass lid 12 is disposed on the substrate 10 to hermetically encapsulate the chip 14, the MEMS element 141 and bonding wires 11.
The illustration of FIG. 1B is disclosed by U.S. Pat. No. 6,303,986, characterized in that a glass lid 12 is disposed on a chip 14 having a MEMS element 141 formed thereon for hermitically encapsulating the MEMS element 141 therein for protection; the chip 14 is disposed on a leadframe 10′ to be carried; the leadframe 10′ is electrically connected to the chip 14 by bonding wires 11; and the bonding wires 11, the lid 12, and the chip 14 are hermetically encapsulated with a packaging material 15.
One common drawback of the above package structures share is that both require the use of a carrier (such as the substrate 10 in FIG. 1A and the leadframe 10′ in FIG. 1B), thereby adversely and undesirably increasing the dimensions of the overall structure and thus failing to comply with the demand for device miniaturization. Consequently, the so-called carrier-free package structures have been developed to counter the profile issue.
As depicted in FIG. 1C, a carrier-free package structure is disclosed by U.S. Pat. No. 7,368,808 characterized in that a glass lid 12 formed with conductive apertures 120 is disposed on a chip 14 having electrical connecting pads 140 and a MEMS element 141 formed thereon for encapsulating the MEMS element 141 therein, wherein the conductive apertures 120 comprise contact pads 122 formed on both sides thereof, the contact pads 122 formed on the inner side being electrically connected to the electrical connecting pads 140 and those formed on the outer side having solder balls 16 formed thereon for allowing the chip 14 to electrically connect with other electronic components via solder balls 16.
In the MEMS package structure depicted in FIG. 1D and disclosed by U.S. Pat. No. 6,846,725, a glass lid 12 formed with conductive apertures 120 is disposed on a chip 14 having electrical connecting pads 140 and a MEMS element 141 formed thereon for hermetically encapsulating the MEMS element 141 therein, wherein the electrical connecting pads 140 further comprise solder bumps 142 and the conductive apertures 120 have contact pads 122 formed on both sides thereof, the contact pads 122 formed on the inner side of the conductive apertures 120 being electrically connected to solder bumps 142 such that the chip 14 can be electrically connected with other electronic components via the contact pads 122 formed on the outer side thereof.
While carrier-free packages are advantageous and favorable for device miniaturization, it nevertheless requires that conductive apertures 120 be fabricated in the lid 12 which then gives rise to issues of high-cost glass drilling and misalignment of the contact pads 122 formed on both sides of conductive apertures 120 or an insecure bonding therebetween, thereby adversely causing inferior electrical connection which in turn degrades the electrical performance of the chip 14 connecting with external electronic components consequently. Therefore, it is desirable to provide a novel package structure that improves on the drawbacks of the prior art as mentioned above.